Verifier to ASIC team

Are you looking for the next step within ASIC verification ? We are currently looking for two ASIC verifiers to help our customer in the telecom sector. You will be involved in new and existing ASIC projects working in teams. The team is currently working on a mix of IP design/verification and different level of SubSys integration/verification. Knowledge and experience: • 3 years or more experience from ASIC verification (we are looking for several experience levels, but 3 years are minimum) • We are looking for a broad scale of experience, but preferable you should have been working with UVM for at least one year • Good command of UVM verification and SystemVerilog • Used to work with complex ASIC and/or large FPGA design • Experience from IP block verification • Multi clock domains • RTL within Verilog, VHDL and/or SystemVerilog • Good English skills, in both speech and writing Meritorious if you have: • Test bench structuring and design • Leadership qualities • RTL design knowledge • Scripting skills • Lab experience • Telecommunication